Nonvolatile semiconductor memory device and method of manufacturing the same

ABSTRACT

According to one embodiment, a nonvolatile semiconductor memory device includes a magnetoresistive element formed on a semiconductor substrate, a first contact plug which extends through an interlayer dielectric film formed on the semiconductor substrate and immediately below the magnetoresistive element, has a bottom surface in contact with an upper surface of the semiconductor substrate, and is adjacent to the magnetoresistive element, and an insulating film formed between the magnetoresistive element and the first contact plug and on the interlayer dielectric film, wherein the insulating film includes a first region positioned on a side of the interlayer dielectric film, and a second region positioned in the insulating film and on an upper surface of the first region, the insulating film is made of SiN, and the first region is a nitrogen rich film compared to the second region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a Divisional application of U.S. Ser. No.14/203,422, filed Mar. 10, 2014, which claims the benefit of U.S.Provisional Application No. 61/875,416, filed Sep. 9, 2013, the entirecontents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a nonvolatilesemiconductor memory device and a method of manufacturing the same.

BACKGROUND

A spin transfer torque MRAM (Magnetic Random Access Memory) including amagnetoresistive element containing a ferromagnetic material as a memoryelement has been proposed (this memory will be called an MRAMhereinafter). This MRAM is a memory that stores information bycontrolling the electrical resistance of the magnetoresistive element intwo states, i.e., a high-resistance state/low-resistance state bychanging the magnetization direction in a magnetic layer by an electriccurrent to be injected into the magnetoresistive element.

The magnetoresistive element includes a memory layer as a ferromagneticlayer having a variable magnetization direction, a reference layer as aferromagnetic layer having an invariable magnetization direction, and atunnel barrier layer as a nonmagnetic layer formed between them.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing a memory cell array of an MRAMaccording to the first embodiment;

FIG. 2 is a plan view showing the memory cell array of the MRAMaccording to the first embodiment;

FIG. 3 is a sectional view taken along a line 3-3′ in FIG. 2;

FIG. 4 is a sectional view showing the first manufacturing step of amagnetoresistive element according to the first embodiment;

FIG. 5 is a sectional view showing the second manufacturing step of themagnetoresistive element according to the first embodiment;

FIG. 6 is a sectional view showing the third manufacturing step of themagnetoresistive element according to the first embodiment;

FIG. 7 is a sectional view showing the fourth manufacturing step of themagnetoresistive element according to the first embodiment;

FIG. 8 is a sectional view of an MRAM according to a modification of thefirst embodiment;

FIG. 9 is a sectional view showing the first manufacturing step of amagnetoresistive element according to the modification of the firstembodiment; and

FIG. 10 is a sectional view showing the second manufacturing step of themagnetoresistive element according to the modification of the firstembodiment.

DETAILED DESCRIPTION

In general, according to one embodiment, a nonvolatile semiconductormemory device includes a magnetoresistive element formed on asemiconductor substrate, a first contact plug which extends through aninterlayer dielectric film formed on the semiconductor substrate andimmediately below the magnetoresistive element, has a bottom surface incontact with an upper surface of the semiconductor substrate, and isadjacent to the magnetoresistive element, and an insulating film formedbetween the magnetoresistive element and the first contact plug and onthe interlayer dielectric film, wherein the insulating film includes afirst region positioned on a side of the interlayer dielectric film, anda second region positioned in the insulating film and on an uppersurface of the first region, the insulating film is made of SiN, and thefirst region is a nitrogen-rich film compared to the insulating film inthe second region.

This embodiment will be explained below with reference to theaccompanying drawings. In this explanation, the same reference numeralsdenote the same arrangements throughout the drawings. However, it shouldbe noted that the drawings are exemplary views, so the relationshipbetween the thickness and the planar dimension, the ratio of thethicknesses of the respective layers, and the like are different fromactual ones. Accordingly, practical thicknesses and dimensions should bejudged by referring to the following explanation. Also, the individualdrawings of course include portions having different dimensionalrelationships and different ratios.

First Embodiment

In the first embodiment, it is possible to deposit an insulating filmthat covers a magnetoresistive element and has a uniform thickness, and,by depositing this insulating film, suppress a leakage current generatedbetween the magnetoresistive element and a contact plug CP connected toa source line.

1. <Overall Configuration Example of MRAM>

An overall configuration example of a nonvolatile semiconductor memorydevice according to this embodiment will be explained with reference toFIGS. 1, 2, and 3. The nonvolatile semiconductor memory device accordingto this embodiment includes an MRAM.

FIG. 1 is a circuit diagram showing a memory cell array of the MRAMaccording to this embodiment.

As shown in FIG. 1, a memory cell in a memory cell array MA includes aseries circuit of a magnetoresistive element 33 and a switching element(e.g., an FET) T.

One terminal of the series circuit (one terminal of the magnetoresistiveelement 33) is electrically connected to a bit line BL, and the otherterminal of the series circuit (one terminal of the switching element T)is electrically connected to a source line SL.

The control terminal of the switching element T, e.g., the gateelectrode of the FET is electrically connected to a word line WL.

A first control circuit 1 controls the potential of the word line WL. Asecond control circuit 2 controls the potentials of the bit line BL andsource line SL.

2. <Details of MRAM>

The structure of the MRAM will be explained in detail with reference toFIGS. 2 and 3.

FIG. 2 is a plan view showing an arrayed arrangement (to be called amemory cell array hereinafter) of the MRAM according to this embodiment.FIG. 3 is a sectional view taken along a line 3-3′ in FIG. 2. Note thatFIG. 3 shows a section of a source line contact 35, in addition to asection of the magnetoresistive element 33.

As shown in FIGS. 2 and 3, the memory cell array MA includes, forexample, a plurality of word lines WL and a plurality of dummy wordlines DWL running in the Y direction, and a plurality of bit lines BLand a plurality of source lines SL running in the X direction. Note thatthe X direction is perpendicular to the Y direction.

Sets each including two word lines WL and one dummy word line DWL arealternately arranged along the X direction.

Also, the bit lines BL and source lines SL are arranged on an activearea AA, and are alternately arranged along the Y direction.

An element isolation region 49 is buried between adjacent active areasAA. That is, the element isolation region 49 and active area AA arealternately formed along the Y direction.

The element isolation insulating layer 49 is formed by, e.g., STI(Shallow Trench Isolation). As the element isolation insulating layer49, an insulating material having a high filling characteristic such assilicon nitride (SiN) is used.

The sectional view will now be explained.

In the memory cell array MA as shown in FIG. 3, an element isolationinsulating layer is formed in the surface region of a p-typesemiconductor substrate (e.g., a silicon substrate) 21, and this regionfunctions as the element isolation region 49.

In the semiconductor substrate 21, a selection transistor T using, e.g.,an n-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor)is formed as the switching element T. The selection transistor T has astructure obtained by forming a recess in the semiconductor substrate21, and burying a gate electrode 20 containing, e.g., polysilicon inthis recess.

More specifically, the selection transistor T includes a gate insulatinglayer 22, the gate electrode 20, and two diffusion layers 25 a and 25 b(a drain-side diffusion layer and source-side diffusion layer).

The gate insulating layer 22 is formed on the inner surface of the lowerportion of the recess formed in the surface of the semiconductorsubstrate 21 and extending in the Y direction.

The gate electrode 20 is formed on the inner surface of the gateinsulating layer 22 so as to fill the lower portion of the recess. Thegate electrode 20 corresponds to the word line WL. An insulating layer24 made of, e.g., SiN is formed on the upper surfaces of the gateinsulating layer 22 and gate electrode 20 so as to fill the upperportion of the recess.

The upper surface of the insulating layer 24 has a height equal to thatof the upper surface of the semiconductor substrate 21 (the uppersurfaces of the diffusion layers 25 a and 25 b to be described below).

The two diffusion layers 25 a and 25 b are formed in the surface of thesemiconductor substrate 21 so as to sandwich the gate insulating layer22, gate electrode 20, and insulating layer 24.

Also, as shown in FIG. 3, the element isolation regions 49 are arrangedon the two ends of the diffusion layers 25 a and 25 b.

Furthermore, an interlayer insulating layer 30 is formed on thesemiconductor substrate 21 (on the insulating layer 24 and diffusionlayers 25 a and 25 b).

A contact plug CP2 is formed in the interlayer dielectric layer 30 onthe diffusion layer 25 a. The contact plug CP2 will be called a BEC(Bottom Electronic Contact) hereinafter.

The BEC is formed in contact with a part of the upper surface of thediffusion layer 25 a and a part of the upper surface of the insulatinglayer 24.

In other words, the BEC and diffusion layer 25 a partially overlap eachother in a plane. This is so because the processing methods of the BECand the diffusion layer 25 a (the recess) are different. The planarshape of the interlayer dielectric layer 30 is, e.g., a square. The BECcontains, e.g., TiN, but the material is not limited to this.

On the diffusion layer 25 b, a contact plug CP1 having a bottom surfacein contact with the diffusion layer 25 b is formed to extend through theinterlayer dielectric layer 30. The contact plug CP1 also extendsthrough an interlayer dielectric layer 31 (to be described later), andhas an upper surface in contact with a source line (55 b (bBL) in FIG.3).

In addition, the magnetoresistive element (to be referred to as an MTJhereinafter) 33 electrically connected to the BEC is formed in theinterlayer dielectric layer 31.

The MTJ is formed in contact with the upper surface of a lower electrode10. The MTJ has, e.g., a circular planar shape, and is formed into apillar shape. Note that in this embodiment, the planar area of themagnetoresistive element 33 and that of the lower electrode 10 have thesame value. However, the planar area of the MTJ is desirably smallerthan that of the lower electrode 10. This makes it possible to bring theentire lower surface of the MTJ into contact with the upper surface ofthe lower electrode 10, and reduce the contact resistance between them.

This MTJ includes a memory layer 11, a tunnel barrier layer 12, and areference layer 13 in this order from below. That is, the memory layer11 is formed on the lower electrode 10 formed on the upper surface ofthe BEC.

The memory layer 11 is a ferromagnetic layer in which the magnetizationdirection is variable, and has perpendicular magnetic anisotropyperpendicular to or almost perpendicular to the film surfaces (uppersurface/lower surface). “The magnetization direction is variable” hereinmentioned means that the magnetization direction changes with respect toa predetermined write current. Also, “almost perpendicular” means thatthe direction of the residual magnetization falls within the range of45°<θ≦90° with respect to the film surfaces.

The tunnel barrier layer 12 is formed on the memory layer 11, and thereference layer 13 is formed on the tunnel barrier layer 12.

The tunnel barrier layer 12 is a nonmagnetic layer, and contains anonmagnetic material such as MgO. However, the material is not limitedto this, and the tunnel barrier layer 12 may also contain a metal oxidesuch as Al₂O₃, MgAlO, ZnO, or TiO.

The reference layer 13 is a ferromagnetic layer in which themagnetization direction is invariable, and has perpendicular magneticanisotropy perpendicular to or almost perpendicular to the filmsurfaces. “The magnetization direction is invariable” herein mentionedmeans that the magnetization direction does not change with respect to apredetermined write current. That is, the magnetization-directionswitching energy barrier of the reference layer 13 is larger than thatof the memory layer 11.

Furthermore, a plurality of insulating films (to be also called amultilayered film hereinafter) are formed along the upper surface andsidewalls (side surfaces) of the MTJ, and along the surfaces (uppersurfaces) of the BEC and interlayer dielectric layer 30. A practicalarrangement of the insulating films will be described below withreference to an enlarged view in FIG. 3. This enlarged view is asectional view in the direction of 3-3′, and shows the periphery of theMTJ in an enlarged scale.

<Insulating Film 14>

An insulating film 14 is formed along the sidewalls of the lowerelectrode 10, memory layer 11, tunnel barrier layer 12, and referencelayer 13. The insulating film 14 is made of silicon-rich SiN. Morespecifically, x and y in Si_(x)N_(y) are set such that the ratio ofsilicon to nitrogen is higher than or close to a reference compositionratio. Practical values of x and y are x=1 and y=1.1.

Also, the thickness of the insulating film 14 is about 1 to 2 nm.

<Insulating Film 15>

In addition, an insulating film 15 is formed along the sidewalls of anupper electrode 17 (to be described later) and the insulating film 14,and along the BEC and interlayer dielectric layer 30.

The insulating film 15 is made of nitrogen-rich SiN. That is, when thereference ratio of x to y in Si_(x)N_(y) is 3:4, the ratio of nitrogento silicon is sometimes close to this reference ratio, and sometimeshigher than the reference composition ratio.

The insulating film 15 is made of a low-conductivity material. That is,the insulating film 15 having a low conductivity can be formed by usingnitrogen-rich SiN.

Furthermore, the thickness of the insulating film 15 on the sidewalldiffers from that of the insulating film 15 on the bottom surface andupper surface. More specifically, the thickness is about 1 to 2 nm onthe sidewall. When formed along the interlayer dielectric layer 30 andBEC, the thickness of the insulating film 15 is about 3 to 4 nm.

Also, the composition ratio of nitrogen in the SiN film changes inaccordance with this thickness difference. More specifically, the ratioof x to y on the upper surface and bottom surface is x=1 to y=1.5, andthe ratio of x to y on the sidewall is x=1 to y=1.3.

As will be described later, this nitrogen-rich SiN can be obtained byperforming plasma nitridation on silicon-rich SiN.

In addition, as shown in FIG. 3, the upper surface of the insulatingfilm 15 formed on the sidewall of the MTJ is higher than the uppersurface of the reference layer 13. However, the arrangement is notlimited to this.

For example, the upper surface of the insulating film 15 formed on thesidewall of the MTJ and the upper surface of the reference layer 13 mayalso be leveled with each other. Note that the upper surface of theinsulating film 15 is sometimes higher than that of the reference layer13 because the reference layer 13 is also etched when an insulating film16 and the insulating film 15 are etched by RIE in Step. 5 (to bedescribed later).

<Insulating Film 16>

Furthermore, an insulating layer 16 is formed to cover the whole MTJ,i.e., along the sidewalls of an upper electrode 17 and the insulatinglayer 15.

Like the above-mentioned insulating layer 14, the insulating layer 16 ismade of silicon-rich SiN. That is, the composition ratio of x to y canalso be the same as that in the insulating layer 14.

Also, the thickness of the insulating film 16 on the sidewall of the MTJdiffers from that of the insulating film 16 on the bottom surface andupper surface of the MTJ. More specifically, the thickness is about 12nm on the sidewall. When formed along the interlayer dielectric layer 30and BEC, the thickness of the insulating film 16 is about 16 to 17 nm.

In FIG. 3, therefore, the value of tsw1 is about 20 nm, and the value oftsw2 is about 14 nm.

In the interlayer dielectric layer 31 as described above, thenitrogen-rich insulating film 15 and silicon-rich insulating film 16 aresequentially stacked on the interlayer dielectric layer 30 with respectto the semiconductor substrate 21.

Note that the multilayered film including the insulating films 15 and 16need not clearly be separated. For example, in the multilayered film, afirst region in which the content of nitrogen is higher than that ofsilicon may exist on the side of the semiconductor substrate 21, and asecond region in which the content of silicon is higher than that ofnitrogen may exist on the side of the interlayer dielectric layer 31.

That is, a region where the composition ratio of nitrogen is higher thanthat of silicon need only exist at least along a path in which the MTJand contact plug CP1 are electrically connected.

The explanation of the arrangement shown in FIG. 3 will be continued.

An upper electrode 17 is formed on the upper surface of the referencelayer 13, and a contact plug CP3 (Top Electronic Contact, to be called aTEC hereinafter) having a bottom surface in contact with the uppersurface of the upper electrode 17 and an upper surface in contact withthe bit line BL is formed.

As described above, the contact plug CP1 extends through the interlayerdielectric layers 30 and 31 and insulating films 15 and 16, and has abottom surface in contact with the upper surface of the diffusion layer25 b . The upper surface of the contact plug CP1 is connected to thesource line (55 b (bBL) in FIG. 3).

Note that of three gate electrodes 20 adjacent to each other in the Xdirection as shown in FIG. 2, two gate electrodes 20 are electricallyconnected to the magnetoresistive elements 33 and function as the wordlines WL, and one gate electrode 20 is not electrically connected to themagnetoresistive element 33 and functions as the dummy word line DWL.

2. <Manufacturing Steps>

The manufacturing steps of the MRAM according to the first embodimentwill be explained below with reference to FIGS. 4, 5, 6, and 7. In thefollowing manufacturing steps, the insulating films 14 to 16 formed tocover the MTJ will be noted.

2.1 <FIG. 4> Step. 1

First, layers are formed up to a BEC buried in an interlayer dielectriclayer 30 by using the well-known techniques.

After that, a metal layer 10, magnetic layer 11, insulating layer 12,and reference layer 13 are sequentially stacked on the interlayerdielectric layer 30 and BEC, and a resist film formed after that ispartially left behind.

Then, the reference layer 13, insulating layer 12, magnetic layer 11,and metal layer 10 are etched by using the resist film as a mask,thereby forming a gate structure shown in FIG. 4. In this step, thecorners of the reference layer 13 of the gate structure are rounded.

Step. 2

Subsequently, while the ambient temperature is set at about 300° C., anSiN film 50 is formed to cover the upper surfaces of the interlayerdielectric layer 30 and BEC and the upper surface and sidewalls of thegate structure by using TSA (Trisilylamine) in RLSA plasma CVD.

Consequently, a silicon-rich SiN film 50 having a uniform thickness isformed to cover the interlayer dielectric layer 30, BEC, and gatestructure.

Note that the ambient temperature is set at about 300° C. because if theSiN film 50 is formed at a temperature higher than 300° C., the metallayer 10, magnetic layer 11, and the like may be damaged.

In this embodiment as shown in FIG. 4, the SiN film 50 has a thicknessequal to a height “h1” on the upper surface of the gate structure and onthe interlayer dielectric layer 30 and BEC, and a thickness equal to awidth “w1” on the sidewalls of the gate structure.

Although the values of “h1” and “w1” are different, the SiN film 50 is aflat film on the sidewalls, upper surface, and bottom surface, i.e., theSiN film 50 is an unbiased film on the film growth surfaces with respectto the structure. This is so because the SiN film is deposited at a lowtemperature of 300° C.

2.2 <FIG. 5> Step. 3

After that, the SiN film 50 as an insulating film 50 is changed(modified) into a nitrogen-rich SiN film 15 by a plasma nitridingprocess. That is, in the composition ratio of x to y described above,the ratio of nitrogen increases compared to silicon. More specifically,the ratio of nitrogen rises to approximately 3:4, or SiN is made ofnitrogen more than this reference value, as described previously.

In this step, the sidewalls are not entirely nitrided, and thesilicon-rich SiN film remains. This film is the insulating film 14described above.

Note that in this plasma nitriding process, the height “h” becomes about3 to 4 nm, and the width “w” becomes about 1 to 2 nm. As describedpreviously, the ratio of nitrogen to silicon in the insulating layer 15formed on the side surfaces of the gate structure is lower than that ofthe insulating film 15 formed on the upper surface of the gate structureand on the BEC and interlayer dielectric layer 30.

2.3 <FIG. 6> Step. 4

In addition, an insulating film 16 is deposited to cover the insulatingfilm 15 by RSLA plasma CVD. Like the insulating film 14, the insulatingfilm 16 is a silicon-rich SiN film.

2.4 <FIG. 7> Step. 5

Then, the insulating films 15 and 16 as prospective formation regions ofan upper electrode 17 are etched by RIE, and a metal film (that becomesan upper electrode 17 later) is buried. An upper electrode 17 is formedby polishing this metal film by CMP.

Furthermore, after an interlayer dielectric layer 31 shown in FIG. 3 isstacked, a through hole extending through the interlayer dielectriclayer 31, insulating film 16, insulating film 15, and interlayerdielectric layer 30 and reaching the diffusion layer 25 b, and aprospective TEC formation region are formed by, e.g., RIE.

After that, a contact plug CP1 and TEC are formed by burying metallayers in the through hole and prospective TEC region. As a consequence,the structure shown in FIG. 3 can be obtained.

As shown in FIG. 7, a distance “1” between the contact plug CP1 and MTJis about 8 to 10 nm.

The distance “1” is smaller than the distance between this MTJ and anadjacent MTJ (not shown).

Effects of First Embodiment

The MRAM according to the first embodiment can achieve effects (1) to(4) below.

(1) The insulating film 15 having a uniform thickness can be deposited.

This will be explained by taking a comparative example in order tofacilitate understanding. This comparative example is a structure inwhich a nitrogen-rich insulating film 15 having a large thicknesscovering the gate structure is deposited in one step instead of Steps. 1to 3 described above. Note that the same reference numerals denote thesame structures.

The characteristic of the nitrogen-rich insulating film 15 has theproblem that a uniform thickness is difficult to obtain on, e.g., theupper surface and sidewalls of the gate structure. For example, theinsulating film 15 is difficult to deposit on a corner formed by theside surface of the metal layer 10 and the upper surface of the BEC, anda domed insulating film 15 like a swelled film is deposited on theinterlayer dielectric layer 30 and on the upper surface of the gatestructure.

By contrast, the insulating film 15 having a uniform thickness can bedeposited in the MRAM according to the first embodiment.

This is so because the embodiment uses the characteristic that asilicon-rich SiN film has a uniform thickness as described above.Accordingly, a silicon-rich SiN film need only be deposited as theinsulating film 15, but this film allows an easy flow of an electriccurrent (has conductivity). This characteristic poses a problem to beexplained in effect (2) below.

In the first embodiment, therefore, a film having a uniform thickness isfirst formed by depositing the silicon-rich SiN film 50, and then aplasma nitriding process is performed. This makes it possible to depositthe nitrogen-rich insulating film 15 having a uniform thickness,although the values of “h” and “w” are different.

(2) A leakage current flowing between the MTJ and contact plug PC1 canbe reduced.

This feature will also be explained by taking a comparative example inorder to facilitate understanding.

This comparative example is a structure in which a single-layered,silicon-rich SiN film is deposited on the upper surface and sidewalls ofthe gate structure, on the BEC, and on the interlayer dielectric layer30 as described above.

As described previously, the deposited insulating film has a uniformthickness.

However, the distance “1” between the MTJ and contact plug CP1 is asshort as about 8 to 10 nm, and a silicon-rich SiN film has conductivityas described above.

In the structure of the comparative example, therefore, when executing,e.g., a data read or write operation, a potential difference is producedbetween the MTJ and contact plug CP1, so an electric current flowingthrough the MTJ flows into the contact plug CP1 through the path betweenthe interlayer dielectric layer 30 and silicon-rich SiN film. Thiscauses an operation error of the nonvolatile semiconductor memorydevice.

By contrast, in the nonvolatile semiconductor memory device according tothe first embodiment, the insulating film 15 is formed between the MTJand contact plug CP1 as shown in FIGS. 3 and 7.

The insulating film 15 has a low conductivity as described previously,and hence can suppress a leakage current such as that generated in thecomparative example. More specifically, the current value can be reducedby about two orders of magnitude from that in the structure of thecomparative example. That is, it is possible to prevent an operationerror of the nonvolatile semiconductor memory device, and improve thereliability of the device.

(3) Deterioration of the MTJ can be prevented.

In the nonvolatile semiconductor memory device according to the firstembodiment, the value of the thickness “w” of the nitrogen-rich SiN filmon the sidewalls is smaller than that of the thickness “h” of thenitrogen-rich SiN film formed on, e.g., the upper surface of the MTJ asmentioned earlier. However, this thickness difference can achieve theeffect of preventing deterioration of the MTJ during the nitridingprocess.

The reasons for this are:

(i) Since the nitriding process has a high energy, the MTJ readilydeteriorates if the nitriding process is performed on the sidewalls ofthe MTJ for a long time period.

(ii) Although the suppression of the leakage current is explained inabove-mentioned effect (2), the insulating film 15 can be deposited atleast on the interlayer dielectric layer 30 and between the MTJ andcontact plug CP1 where a leakage current is readily generated.

For reasons (i) and (ii) above, deterioration of the MTJ can beprevented more when the value of the thickness “w” of the insulatingfilm 15 formed on the sidewalls is smaller than that of “h”.

(4) The parasitic capacitance can be reduced.

In the nonvolatile semiconductor memory device according to the firstembodiment, the parasitic capacitance between adjacent MTJs can bereduced.

The dielectric constant of a nitrogen-rich SiN film is higher than thatof a silicon-rich SiN film. That is, if the thickness “w” on thesidewalls of adjacent MTJs is large, the parasitic capacitance increasesbetween these adjacent MTJs. This may change data held in these MTJs.

By contrast, in the nonvolatile semiconductor memory device according tothe first embodiment, the parasitic capacitance between adjacent MTJscan be reduced because the thickness “w” on the sidewalls is small.

Note that the same effect can be achieved for the parasitic capacitancebetween the MTJ and contact plug CP1.

<Modification>Next, a nonvolatile semiconductor memory device accordingto a modification of the first embodiment will be explained withreference to FIGS. 8, 9, and 10.

This modification is a structure in which the insulating film 14 isexcluded from the above-mentioned first embodiment. Only an arrangementdifferent from the first embodiment will be explained below.

1. <Details of MRAM>

FIG. 8 shows the section of a memory cell array according to themodification. FIG. 8 is a sectional view taken along a line 3-3′ in FIG.2.

As shown in FIG. 8, an insulating film 15 is directly formed along anupper electrode 17, reference layer 13, tunnel barrier layer 12, memorylayer 11, lower electrode 10, BEC, and interlayer dielectric layer 30.

The insulating layer 15 has a thickness of about 1 to 2 nm on thesidewalls, and a thickness of about 3 to 4 nm on the BEC and interlayerdielectric layer 30.

In addition, an insulating film 16 is formed to cover the insulatingfilm 15.

2. <Manufacturing Steps>

Manufacturing steps according to the modification will now be explainedwith reference to FIGS. 9 and 10. Note that an explanation of the samesteps as those of the nonvolatile semiconductor memory device accordingto the first embodiment will be omitted.

2.1 <FIG. 9> Step. 11

First, as shown in FIG. 9, an insulating film 15 made of nitrogen-richSiN is deposited along an upper electrode 17, reference layer 13, tunnelbarrier layer 12, memory layer 11, lower electrode 10, BEC, andinterlayer dielectric layer 30 by using RSLA plasma CVD.

Note that the insulating film 15 is deposited in one step in thenonvolatile semiconductor memory device according to the modification,but the film thickness differs from the thickness of the insulating film15 of the comparative example described in effect (1) of the firstembodiment. That is, since the insulating film 15 of the modificationhas a thickness equivalent to that of the first embodiment, so theproblem explained in the comparative example of effect (1) does notoccur in this modification.

2.2 <FIG. 10> Step. 12

After that, an insulating film 16 is deposited as shown in FIG. 10, andthe structure shown in FIG. 8 is obtained through the step explainedwith reference to FIG. 7.

<Effects of Modification>

Even the nonvolatile semiconductor memory device according to thismodification can achieve effects (1) to (4) of the above-mentioned firstembodiment, and can also achieve effect (5) below.

(5) The number of manufacturing steps can be reduced.

When manufacturing the nonvolatile semiconductor memory device accordingto the modification, Steps. 2 and 3 described previously can be omitted.That is, it is possible to reduce the manufacturing cost while obtainingeffects (1) to (4).

Note that as explained in the first embodiment and its modification, itis desirable to uniformly deposit the insulating film 15 on the entiresurface of the MTJ in order to suppress the leakage current between theMTJ and contact plug CP1.

While certain embodiments have been described, these embodiments havebeen presented by way of example only, and are not intended to limit thescope of the inventions. Indeed, the novel embodiments described hereinmay be embodied in a variety of other forms; furthermore, variousomissions, substitutions and changes in the form of the embodimentsdescribed herein may be made without departing from the spirit of theinventions. The accompanying claims and their equivalents are intendedto cover such forms or modifications as would fall within the scope andspirit of the inventions.

What is claimed is:
 1. A nonvolatile semiconductor memory devicemanufacturing method comprising: forming a magnetoresistive element on asemiconductor substrate; forming a first insulating film along an uppersurface and sidewall of the magnetoresistive element and along aninterlayer dielectric layer formed immediately below themagnetoresistive element; forming a second insulating film which isnitrogen-rich compared to the first insulating film by plasmanitridation to the first insulating film; depositing a third insulatingfilm on the second insulating film; and forming a contact plug whichextends through the third insulating film, the second insulating film,and the interlayer dielectric layer, and has a bottom surface in contactwith an upper surface of the semiconductor substrate.
 2. The methodaccording to claim 1, wherein each of the second insulating film and thethird insulating film is made of SiN.
 3. The method according to claim2, wherein a thickness of the insulating film formed on the uppersurface and the interlayer dielectric layer is larger than that of theinsulating film formed on the sidewall.
 4. The method according to claim3, wherein the thickness of the insulating film formed on the uppersurface and the interlayer dielectric layer is 3 to 4 nm, and thethickness of the insulating film formed on the sidewall is 1 to 2 nm. 5.The method according to claim 1, wherein the second insulating filmformed on the sidewall has a dielectric constant higher than that of thethird insulating film.